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When implementing a mux, use either an assign statement with ternary operators, or case statements. 

assign statement with ternary operator 

assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a );

case statements

we need always block here to implement the mux using case statements

ex. always @ ( a or b or c or d or sel) begin 

case (sel)

2'b00 : out <= a; 

2'b01: out <= b; 

2'b10: out <= c;

2'b11: out <= d; 

endcase

end


December 19th 2023
Reading up on this article: 

https://www.verilogpro.com/systemverilog-always_comb-always_ff/ 

  https://www.verilogpro.com/verilog-always-block/